Business and consumers use a wide array of wireless devices, including cell phones, wireless local area network (LAN) cards, global positioning system (GPS) devices, electronic organizers equipped with wireless modems, and the like. The increased demand for wireless communication, and other mobile devices has created a corresponding demand for technical improvements to such devices. Generally speaking, more and more of the components of conventional radio receivers and transmitters are being fabricated in a single integrated circuit package.
One important aspect of wireless communication devices having integrated circuits is battery life. In order to maximize battery life for these wireless communication devices, much emphasis has been placed on minimizing power consumption in the integrated circuits of the wireless communication devices.
Conventional approaches to minimizing power consumption in integrated circuits include voltage scaling. Voltage scaling is useful for minimizing dynamic power consumption due to switching. However, voltage scaling does not provide much, if any, benefit for static power consumption due to leakage current. This causes problems in digital technologies that have been scaled to be smaller and smaller, resulting in more leaky circuits. In fact, the leakage current, which used to be a relatively small component of total power consumption, is actually dominating total power consumption for many deep submicron digital chips. A digital chip with several million transistors, for example, may have a DC leakage current of several milliamps, or even tens of milliamps, when the chip is in a standby mode. In typical mobile devices, this amount of leakage current, and its corresponding power consumption, is unacceptable.
Conventional approaches to minimizing power consumption in integrated circuits also include threshold scaling. Threshold scaling is useful for minimizing static power consumption due to leakage current. However, threshold scaling does not provide much, if any, benefit for dynamic power consumption due to switching.
Thus, in order to make use of both voltage scaling to minimize dynamic power consumption and threshold scaling to minimize static power consumption, one approach has been to incorporate switching software into the chip. This switching software determines the voltage and threshold needed to operate a particular task and switches the chip into a corresponding mode while that task is being performed. One drawback to this approach includes the use of a safety margin in the calculation of critical path delays when selecting the mode, which results in the chip possibly not operating at its optimum potential.
One recent solution to this problem uses adaptive voltage scaling and adaptive threshold scaling cooperatively based on a clock frequency for the corresponding chip as measured on the chip. With this approach, adaptive voltage scaling may be used to minimize dynamic power consumption at higher frequencies, while adaptive threshold scaling may be used to minimize static power consumption at lower frequencies, without the use of an arbitrary safety margin for critical path delays. This results in a minimization of average power consumption over all operating modes, which maximizes the battery life for the mobile device. However, leakage current in the active or operating mode remains a problem with this approach and limits the battery life.
One solution to the problem of leakage current was proposed in “Standby Power Management for an 0.18 μm Microprocessor,” L. Clark et al., ISLPED02, 2002. This solution provides for moving the bulk relative to the source in transistors of the integrated circuit, while the sources are fixed at the supply rails. For p-channel devices, the bulk (or back) bias is derived from an additional power supply and the bias is developed from a linear regulator. On the negative rail, there are two conflicting references: one to a back bias generated by a charge pump and another that moves the source positive with respect to ground with a linear regulator. Both of these techniques are performed on-chip and suffer from process-inherent sensitivities, in addition to low quality analog process attributes of deep submicron processes such as leakage noise matching and the like. Also, because this approach is on-chip, an inability to easily scale for new technology is another disadvantage. Also, the use of a linear regulator does not allow total system power savings afforded by an external switching regulator.